1. Field of the Invention
The embodiments of the invention generally relate to complementary metal oxide semiconductor body (CMOS) devices and, more specifically, to a CMOS structure and method of forming the CMOS structure with dual metal gates to suppress corner leakage.
2. Description of the Related Art
As complementary metal oxide semiconductor (CMOS) devices are scaled in size, conventional gate stack structures are being replaced by metal gate stack structures. Specifically, a conventional gate stack structure typically includes a thin silicon oxide (SiO2) gate dielectric layer and a doped-polysilicon gate conductor layer. Unfortunately, doped polysilicon gate conductor layers are subject to depletion effects. These depletion effects result in an increase in the effective gate dielectric layer thickness and, thereby limit device scaling. Thus, high k dielectric layer-metal gate conductor layer stacks with different work functions for N-type field effect transistors (NFETs) and p-type field effect transistors, have been introduced. These stacks are improvements over the conventional gate structures in that the high k-dielectric layer minimizes leakage current and the metal gate conductor layer is not subject to depletion effects. However, with ever narrower channel widths new concerns for future CMOS technology generations and, more particularly, for CMOS technology generations at or beyond the 65 nm node are introduced even with such high-k dielectric layer-metal gate conductor layer stacks.